Electromagnetic Crosstalk Analysis and Signoff Tools for System on Chip Designs

Helic provides Electronic Design Automation (EDA) software that mitigates the risk of Electromagnetic Crosstalk in high-speed and low-power System on Chip (SOC) Designs. Since 2000, Helic cutting-edge technology enabled analog/RF and high-frequency IC design engineers to synthesize inductive devices and model electromagnetic and parasitic phenomena with accuracy, speed and seamless design flow interoperability. In the last few years, as frequency, bandwidth and level of integration continue to escalate, Helic tools are being used by top semiconductor companies to debug and analyze electromagnetic crosstalk issues in their advanced SOC designs.  These designs span leading market applications such as wireless communications, automotive, high-speed computing, networking, and Internet of Things (IoT)

Why choose
Helic

  • Crosstalk Signoff to avoid costly silicon spins and market delays
  • Extract RLCk parasitics of complex layouts with the highest capacity engine
  • Capture Electromagnetic Crosstalk across design hierarchy in complex SOCs
  • Ability to Model everything accurately
  • Synthesize any spiral inductor design
  • Enable RF and Processor integration on the same die

Our Products

VeloceRF

INDUCTOR SYNTHESIS & MODELING

Synthesize DRC clean devices down to 10nm CMOS and model coupling among inductors.

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RaptorX

ELECTROMAGNETIC MODELING

Calculate pre-LVS electromagnetic parasitics for highly complex devices and circuitry such as power grids, full custom blocks, spiral inductors and clock trees.

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Exalto

POST-LVS RLCK EXTRACTION

Identify the root cause of crosstalk including electrical, magnetic and substrate coupling among different blocks in the design hierarchy.

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