Electromagnetic Crosstalk Analysis and Signoff Tools for System on Chip Designs

Have You Experienced Inexplicable
Chip Failure?

  • Your silicon has unpredictable timing failure, even after passing your EDA timing tool analysis
  • Your silicon fails to operate at target speed
  • Your silicon goes into full-chip reset due to inexplicable logic error
  • Your design has high speed digital core and RF/analog blocks on the same substrate
  • Your EDA tools cannot perform full-chip RLCK extraction

Helic Introduces Pharos

Pharos diagnoses or uncovers EM crosstalk risk, reduces design failures and improves design productivity

Helic’s new tool helps designers uncover and highlight nets that are susceptible to EM crosstalk in their design, combining industry’s largest capacity EM extraction engine with proprietary high-performance simulation technology.

Helic provides Electronic Design Automation software that mitigates the risks of electromagnetic crosstalk, induced performance degradation, and failure in high-speed and low-power System-on-Chip designs.

Helic Advantage Pushing the limits of frequency and capacity in SoC designs

Why choose
Helic

  • Synthesize rapidly any spiral device
  • Capture electromagnetic effects across hierarchy
  • Optimize the silicon floor plan
  • Enable RF & Processor integration on the same die
  • Extract RLCk parasitics with the highest capacity engine

Our Products

Pharos

Electromagnetic Crosstalk Diagnosis

Pharos enables designers to uncover and highlight nets that are susceptible to EM crosstalk in their design.

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VeloceRF

INDUCTOR SYNTHESIS & MODELING

Synthesize DRC clean devices down to 10nm CMOS and model coupling among inductors.

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RaptorX

EARLY ELECTROMAGNETIC ANALYSIS

Pre-LVS electromagnetic modeling and analysis of highly complex devices and circuitry.

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Exalto

ELECTROMAGNETIC ANALYSIS & SIGNOFF

Post-LVS electromagnetic analysis and signoff software for highly complex system-on-chip designs.

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ARRANGE YOUR DEMO AT DAC 2018

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