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ATHENS, GREECE - Helic S.A. announces today the commercial release of VeloceRF™, its revolutionary EDA tool that enhances popular industry design environments to enable delivery of first pass RF ICs and systems-in-package, significantly shortening the development cycle for complex wireless transceiver products.
VeloceRF™ constitutes a major step forward in true RF IP portability and design re-use; by enabling rapid and accurate inductor modeling -- including mutual inductance -- as well as inductor synthesis inside the flow, it supports whole-chip modeling of RF ICs without reliance on pre-characterized inductor models. VeloceRF-generated models of RF IP blocks are available throughout the design flow, providing designers with netlists fully-loaded with electromagnetic effects and parasitics and enabling them to rapidly customize and optimize RF performance.
VeloceRF™ is the outcome of many years of research and true silicon validation, with some 3,000 inductive structures and several RF circuits in more than 10 different foundry silicon processes tested by Helic and its customers around the world.
VeloceRF™ compresses RF IC development time dramatically. Helic's RF IP portfolio offers customers a library of working silicon test cases developed in record time. Example circuits include SiGe BiCMOS LNAs, power amps for 802.11a/b, VCOs for GSM 1800/1900 and passive CMOS mixers with in-package baluns, most of which were taped-out in just 10 days from project start!
To make this capability easily accessible, VeloceRF™ seamlessly interfaces with third-party schematics and layout editors, also tapping to parasitics extraction (RCX) and layout-vs.-schematic (LVS) tools. Through an automated layout synthesis feature, Spiral Wizard™, the tool can generate constraint-driven layouts for all kinds of spiral inductor devices (square, rectangular, octagonal), or even multi-inductor structures such as transformers, baluns and differential inductors.
VeloceRF™ is based on an efficient modeler that supports complete RLCk extraction of RF passives, particularly calibrated for silicon-integrated spiral-type inductive elements and high-frequency interconnect lines. The modeler takes into account the effects of the substrate underneath and around a spiral inductor and can easily interface with specialized substrate analysis tools. The tool also supports the design of embedded passives in advanced packaging substrates like LTCC and BT.
The software is currently available as a module within the Cadence Virtuoso® platform, compatible with both Sun/Solaris® and Linux operating systems.
Dr Yorgos Koutsoyannopoulos, Helic's CEO, commented on VeloceRF's release: "With VeloceRF™ we are introducing a novel EDA tool that addresses RF designers' needs for rapid, whole-chip RF modeling, RF IP portability and re-use. We chose first to integrate our solution seamlessly with Cadence's industry-leading Virtuoso® platform but we intend to build interfaces to other platforms as well."
Further Koutsoyannopoulos emphasized the key benefits of the product: "We add significant value to our customers' investment in EDA platforms, while boosting time-to-market and slashing development costs by more than 50% in complex RF transceiver designs. By enabling fully-loaded electromagnetic modeling at a blazing-fast speed, VeloceRF™ can help prevent inductance-related failures early in the cycle and avoid costly re-spins which are all too often in RF and high-speed IC development. The net benefit from using VeloceRF™ can exceed $1 million for a demanding transceiver design. Helic will also provide blocks of RF IP developed with VeloceRF™ to jump-start customer projects. Bringing VeloceRF™ to the market we intend to elevate RF IC and systems-in-package design from an exotic art to a systematic design process."
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