CITATIONS

A heterogeneous contactless transceiver circuit is designed to provide inter-tier signalling for a 3-D system considering specific bonding constraints. The system is composed of two tiers, a 65 nm processing tier and a 0.35 µm sensing tier. Face-to-back integration is chosen to support fluidic sensing. Half duplex communication between the tiers is provided through inductive links. Each tier is considered to be fabricated in a different technology to enable low manufacturing cost and benefit from the advantages each technology offers. Both the uplink and downlink transceivers achieve data rates that reach 1 Gbps with non-return-to-zero data encoding. Energy efficiency is the predominant objective, with the uplink dissipating 5.28 pJ/b and 8.67 pJ/b for the downlink. A 6.8× power reduction is demonstrated when using heterogeneous technologies, compared to a state-of-the-art 0.35 µm transceiver, while the dissipated energy is decreased by 37.5% as compared to a state-of-the-art 65 nm transceiver. Process variation analysis is also performed to ensure the proposed circuit operates correctly across several process corners, covering a broad design space. To improve system robustness, an overhead of 2.3% on the peak power and <1% on the average power is shown, respectively.

Date 03/04/2018 Pubisher ELSEVIER Pubished in Integration Page VOLUME 62, 329-340 DOI  https://doi.org/10.1016/j.vlsi.2018.04.001

A heterogeneous contactless transceiver circuit is designed to provide half duplex communication for a 3-D system considering specific bonding constraints. The system is composed of two tiers and is integrated face-to-back to support fluidic sensing. Communication between the tiers is achieved through inductive links. Each tier is considered to be fabricated in a different technology node to enable low manufacturing cost and benefit from the advantages each technology offers. Both the uplink and downlink transceivers achieve data rates that reach 1 Gbps with non-return-to-zero data encoding. Energy efficiency is the primary objective, with the uplink dissipating 4.93 mW and the downlink 10.53 mW. A 5.2 × power reduction is achieved when using heterogeneous technologies, compared to a state-of-the-art 0.35 βm transceiver, while the dissipated energy is decreased by 34% as compared to a state-of-the-art 65 nm transceiver.

Date 28/09/2017 Pubisher IEEE Pubished in IEEE

A digital polar transmitter is introduced using 9-b thermometer-coded uniform cells to achieve high linearity for wideband signal. A 960 MHz delay tuner is designed for precise amplitude and phase alignment. An on-chip DC-DC is included for direct battery connection and output power control. Boosted bias improves PA efficiency at low power region. This digital polar transmitter outputs peak power 21.9 dBm with 41% drain efficiency, achieves EVM -30.7dB with 802.11ac compliance of 20 MHz 256-QAM signal, also 4.5%/4.8% with LTE-A 40 MHz carrier aggregation compliance of 64-QAM signal.

An integrated passive power combiner is discussed and characterized based on test structure fabricated in a 150 nm LFoundry CMOS process. The power combiner uses differentially driven coupled transformers as a basic building block. We discuss first the constraint driven sythesis of the transformer itself and the device modeling with a rapid RLCk model extractor. Helic’s electronic design automation (EDA) tools are used for both, synthesis and extraction of the passive devices. The accuracy of the extracted transformer model is proven by comparison to an EM tool. The fabricated power combiner structure is finally extracted with the same EDA toolset and compared to measured data from on-wafer experiments. Good agreement is achieved in all cases proving the accuracy of the proposed synthesis and extraction methodology for complex RF IC designs.

Date 29/12/2014 Pubisher IEEE Pubished in IEEE DOI https://doi.org/10.1109/EuMIC.2014.6997780