Meet us @ the TSMC Open Innovation Platform® (OIP) Ecosystem Forum 2017 in Santa Clara to find out how the Wipro/NXP High-Speed SerDes Analog & Mixed-signal Design Team uses VeloceRF and RaptorX to design a high-speed multi-protocol 28Gbps SerDes design with TSMC 16FFC.
Wed. 09.13, 11:35
June 20, 2017
Helic @ Samsung Theater, DAC 2017
Helic presents a new set of tools and a design methodology that answers the next-generation EM problems spanning across the entire SoC. Discover "EM crosstalk analysis and signoff on 14/10nm CMOS" at DAC 2017, Samsung theatre, Austin Convention Center.
Is your jitter out-of-spec? Is analog/digital interference ruining their performance of your chip? Do you suffer from crosstalk on your high-speed links?
Helic presents a new set of tools and a design methodology that answers the next-generation EM problems spanning across the entire SoC. Discover "Electromagnetic Crosstalk Analysis and Signoff with Helic and Calibre" at DAC 2017, Mentor booth, Austin Convention Center.
Mon. 06.17, 13:00
Seating is limited, register at https://www.mentor.com/events/design-automation-conference/schedule?fa=ic-design---test