PRESS RELEASES

  • EM Signoff tool, Pharos, introduced at Samsung’s Theatre During DAC June 26, 2018

    Whenever a company invites you to participate in their marketing events, it’s a testimony to the technology and the value you add as a partner. And when that partner is the #1 Semiconductor by revenue world-wide, it is an exceptional honor. At times like these, you better have something of high value to present. To […]

  • Helic Certified by GLOBALFOUNDRIES for 22FDX® Process Technology

    Certification Enables Electromagnetic Modeling Engine, Crosstalk Analysis and Signoff Tools Highlights: Helic’s electromagnetic modeling engine and RaptorX tool have been qualified on GF 22FDX® process. SANTA CLARA, CA – July 9, 2018, Helic, Inc. announced today that its electromagnetic (EM) modeling engine and RaptorX™ have been certified for GLOBALFOUNDRIES 22nm FD-SOI (22FDX®) process technology, enabling […]

  • Goodix Accelerates the Development of Innovative Biometric Solutions with Helic Unified Electromagnetic-Aware Design Flow

    Helic EM-aware flow and tools have been integrated into Goodix mixed signal design environment. This integration enables Goodix designers to accelerate their pace of innovation and improve the robustness of their designs. Goodix, and Helic, Inc. today announced that the companies have collaborated to integrate Helic’s VeloceRF™ RF device synthesis, RaptorX™ EM modeling and Exalto® […]

  • Helic Introduces Pharos, a New Tool for Electromagnetic Crosstalk Risk Analysis

    SANTA CLARA, Calif.–(BUSINESS WIRE)–Helic, Inc., the industry-leading provider of electromagnetic crosstalk solutions for System-on-Chips (SOCs), today announced Pharos to help designers identify and alleviate high-risk areas for electromagnetic (EM) and substrate crosstalk induced failures. Pharos combines industry’s largest capacity EM extraction engine with proprietary high-performance simulation technology, allowing designers to quickly uncover and highlight nets […]

  • HSPICE SIG 2018 event

    Helic was invited to participate in the HSPICE SIG 2018 event at the Santa Clara Marriott that was held on Jan 31 2018. The event was well attended by key designers and design managers from the high speed digital and mixed signal design community. Helic’s message regarding the importance of chip-level EM aware physical verification […]

  • Helic Appoints Tom Flynn as Vice President of Sales

    Helic, Inc., an industry-leading provider of electromagnetic crosstalk solutions has appointed Tom Flynn to the executive management team as the Vice President of Sales. Tom brings more than 18 years of global sales leadership in the electronic design automation (EDA) industry. Most notably, Tom led Ansoft’s global sales team for over a decade, tripling sales […]

  • Synopsys and Helic Deliver Unified Electromagnetic-Aware Analog and RF Custom Design Flow

    Highlights: Synopsys Custom Compiler has been integrated with Helic’s RF device synthesis, EM parasitic extraction, and modeling software Integrated solution blends parasitics from Synopsys’ StarRC and Helic’s 3D RLCK extraction into a unified netlist for EM analysis Comprehensive RF simulation and analysis features in Synopsys’ HSPICE and Custom WaveView enable robust design verification and analysis […]

  • MTV Conference Presentation: SOC Electromagnetic Cross talk – Is it Real? Symptoms and Test cases

    A MTV presentation by Anand Raman, Yorgos Koutsoyannopoulos, Padelis Papadopoulos, Konstantis Daloukas, Thomas Flynn and Magdy Abadir (Helic). The 18th annual workshop on Microprocessor and SOC Test and Verification was held in Austin, TX on Dec 11-12, 2017. General Chair: Magdy S. Abadir Vice General Chair: Li-C. Wang, University of California at Santa Barbara Program […]

  • Semi Engineering: The Trouble with Models

    Models are becoming more difficult to develop, integrate and utilize effectively at 10/7nm and beyond as design complexity, process variation and physical effects add to the number of variables that need to be taken into account. Modeling is a way of abstracting the complexity in various parts of the semiconductor design, and there can be […]

  • Nautech announces collaboration with Helic, first customer win in the Russian semiconductor market

    Moscow (Russia), August 21, 2017 – NAUTEСH Corporation, the exclusive representative for Helic, Inc in Russia and the CIS countries, announces the first customer win for Helic’s Electronic Design Automation (EDA) software tools. After a thorough technical evaluation, the prestigious Scientific Research Institute for System Analysis of Russian Academy of Sciences (SRISA) decided to use […]

  • Helic in DeepChip.com

    Helic banners are advertised on John Cooley’s Deepchip website  http://www.deepchip.com/ Please visit and check the latest banners from Helic.

  • Analog/RF Chip Design Expert Helic Joins ESD Alliance

    Redwood City, CA, February 23rd, 2017 – Helic, a leading supplier of Electronic Design Automation (EDA) software for crosstalk analysis and signoff of high-frequency analog/RF and high-speed system-on-chip (SoC) design, today became a member of the Electronic System Design Alliance (ESD Alliance) after its 10-member board approved Helic’s membership application. “The ESD Alliance plays an important […]

  • Helic sponsors IEEE CICC Student Scholarship Award

    SAN FRANCISCO, CA — Helic, Inc., the technology leader in EDA solutions for RF and high-speed IC design, was a proud sponsor of the Student Scholarship Award at the 2011 IEEE Custom Integrated Circuits Conference (CICC) in Silicon Valley. The IEEE Custom Integrated Circuits Conference is a premier conference devoted to IC development, design challenges […]

  • Scintera Networks and Helic sign multiyear agreement

    SAN FRANCISCO, CA, November 3, 2011 — Helic Inc., the technology leader in EDA solutions for high-speed IC design and Scintera Networks, Inc., a leading provider of mixed signal semiconductors for wireless communications announce a multiyear partnership, with the integration of Helic’s VeloceRF™ and VeloceRaptor/X™ in Scintera’s RFIC design flow. VeloceRF™ features a unique component-synthesis […]

  • Freescale Semiconductor selects Helic’s tools for RF IC design flow

    SAN FRANCISCO, CA (June 3, 2011) — Helic, Inc., the technology leader in EDA solutions for RF and high-speed IC design proudly announces that FREESCALE SEMICONDUCTOR selected Helic’s VeloceRF™ and VeloceRaptor/X™ to be part of their RFIC design flow. To meet the demands of RF and high-speed design in advanced silicon processes, VeloceRF™ features a […]

  • Visit Helic at DAC 2010

    Helic, Inc., the technology leader in inductor synthesis and extraction solutions for Analog/RF and high-speed IC design welcomes you to visit our booth at DAC and attend live demos of Helic’s latest product releases. Take the opportunity to meet with our technology experts and discuss how Helic’s products can help you make your designs more […]

  • Helic launches Designers’ Forum

    SAN FRANCISCO, CA May 19, 2010 — Helic Inc., the technology leader in inductor synthesis and extraction solutions for RF and high-speed IC design, has created a Designer’s Forum hosted in its website at http://www.helic.com/forum. Designers, CAD engineers and EM modeling professionals are welcome to join a community of experts and exchange views on design matters […]

  • Helic’s VeloceRF™ Qualified by TSMC for high-speed and RF design at 65nm

    SAN FRANCISCO, CA, Aug. 06, 2009 — Helic, Inc. today announced that TSMC has qualified its VeloceRF tool as part of TSMC’s Electromagnetic (EM) Tool Qualification Program. VeloceRF has been accuracy-certified against TSMC’s 65nm silicon-verified spiral inductor set. TSMC’s EM Tool Qualification Program assists IC designers by providing certified process technology files, layout and measurements […]

  • ClariPhy leverages Helic’s VeloceRF™ EDA tool for first-pass success of CMOS 10G mixed-signal IC

    IRVINE, Calif., and ATHENS, Greece, June 4, 2007 – ClariPhy Communications and Helic S.A. today announced details of their joint engineering collaboration over the past 12 months, which has been instrumental in the first-pass success of ClariPhy’s single-chip, 10GBASE-LRM, mixed-signal CMOS transceiver. ClariPhy’s transceiver features a low-power 10G Analog to Digital Converter (ADC) and a […]

  • Helic’s VeloceRF™ is selected by Fujitsu to build RFIC design flows for sub-100nm CMOS processes.

    ATHENS, GREECE, June 4, 2007 – Helic S.A. proudly announces that Fujitsu Limited has adopted VeloceRF™ and Helic’s technology to build a new design-flow for RFICs in its 90nm and 65nm CMOS processes. The parties have agreed to develop world-class tooling and design methodology to support rapid prototyping and volume production of high-frequency ICs applying […]

  • New release of VeloceRF™ supports 90-nm & 65-nm RFIC design

    ATHENS, GREECE – Helic S.A. announces today the commercial availability of VeloceRF™ v1.5, featuring an enhanced Spiral Wizard™ inductor synthesizer, several improvements in its rapid RLCK modeling engine and new features addressing Design for Manufacturability (DFM) for 90-nm and 65-nm RFICs. The Spiral Wizard™ synthesis engine in VeloceRF v1.5 now supports the creation of patterned […]

  • New release of VeloceRF™ supports 90-nm & 65-nm RFIC design

    ATHENS, GREECE – Helic S.A. announces today the commercial availability of VeloceRF™ v1.5, featuring an enhanced Spiral Wizard™ inductor synthesizer, several improvements in its rapid RLCK modeling engine and new features addressing Design for Manufacturability (DFM) for 90-nm and 65-nm RFICs. The Spiral Wizard™ synthesis engine in VeloceRF v1.5 now supports the creation of patterned […]

  • AWR and Helic Partner to Offer VeloceRF Technology in Analog Office Software

    EL SEGUNDO, Calif. and ATHENS, Greece – July 17, 2006 – Applied Wave Research, Inc. (AWR®) and Helic S.A. (Helic®) today announced a technology licensing agreement that enables the integration of Helic’s VeloceRF™ whole-chip radio frequency (RF) extraction, modeling, and verification technology into AWR’s Analog Office® RF integrated circuit (IC) design suite. The companies also announced […]

  • Helic® and EdXact collaborate to boost RFIC design

    ATHENS, Greece – GRENOBLE, France, November 16, 2005 – Helic S.A. and EdXact S.A. leading European EDA companies in modeling and verification, announce today a joint development that will result in an extension of Helic’s VeloceRF™ inductance modeling, verification and synthesis tool. The new offering, called VRFJ™, will be based on EdXact’s Jivaro™ netlist reduction technology. Marketed […]

  • Micro Linear selects Helic’s VeloceRF™ for RFIC inductor synthesis modeling and verification

    ATHENS, GREECE, June 8, 2005 – Helic S.A. proudly announces that another semiconductor company has selected its VeloceRF EDA product. Micro Linear Corporation (Nasdaq: MLIN), a leading digital wireless transceiver U.S. company, will be using VeloceRF for synthesis, modeling and verification of integrated inductors in its RFIC designs. Silicon-integrated wireless designs and shrinking process geometries […]

  • Helic introduces unique new features in the VeloceRF™ toolset

    The Spiral Wizard™ module within VeloceRF v1.4.2 can rapidly and efficiently deliver spirals “to-order”, tailored exactly to the designer’s requirements in inductance, operating frequency and quality factor. The design process is significantly simplified and accelerated, as it is disentangled from the use of pre-characterized inductor libraries. The Spiral Wizard features on-the-fly layout synthesis, under an […]

  • Helic and Cadence Collaborate to Deliver RF Design Solution

    ATHENS, GREECE – Helic S.A. announces a multi-faceted IP and EDA tools collaboration with Cadence Design Systems, Inc. in which both companies aim to become the springboard for the design of next-generation wireless semiconductor products. As part of the agreement, VeloceRF™, Helic’s recently introduced tool for the rapid modeling and synthesis of on-chip and in-package […]