Helic.com Forum

LTCC module design flow

2010-03-16T19:42:13Z

An earlier work on the subject, which describes a hardware demonstrator we developed a few years back to validate the concepts…

Editing symbols created by VeloceWired

2010-04-24T21:10:28Z

I would like to edit the symbol created during the model extraction step in VeloceWired. However I am unable to do so. Can you please explain how one can edit the symbol?

Available Bondwire Profiles in VeloceWired

2010-04-12T10:35:32Z

VeloceWired supports the widely used jedec-4 and jedec-5 formats, and also two types of generic format. The combination of jedec and generic types allows the user to efficiently approximate practically any type of bondwire (die-package, downdonds,die-die, stacked dies bonding, etc.).

For each bondwire profile several geometrical and physical parameters, such as diameter, height, angles, resistance can be defined, resulting in different model.

Bondwire Modeling

2010-04-12T10:23:21Z

VeloceWired features a rapid EM modeling engine, based on closed-form expressions that extract distributed netlists to model the performance of bondwire interconnects. Bondwire segments are represented as 3D vectors, and appropriate RLCk models are extracted.

The procedure enables rapid and accurate modeling of complex EM effects like:
- self inductance & resistance
- mutual inductance
- high frequency resistance (Skin Effect)
- capacitive coupling

An additional feature is the annotation of inductance values back into the layout. This is extremely useful as it provides the designer with an immediate “feeling” of what has been drawn so far. Thus the designer can easily quick-fix certain wires that are likely to hinder the circuit’s performance (e.g. too long wires that introduce large inductance, parallel wires with undesired magnetic coupling, etc).

Multi-die bonding

2010-04-12T10:07:42Z

I have a case of two dies that must be bonded in the same package. Also there are a lot of downbonding wires. Can i use VeloceWired for such an application?

Thanks

Compact Modeling with Guaranteed Passivity

2010-01-20T12:38:51Z

At the latest MOS-AK workshop that fringed the ESSCIRC/ESSDERC conference in Athens, I gave the following paper which provides a good overview of our unique modeling methodology and discusses model passivity and compaction issues.

Please find it on the MOS-AK web site in this link.

importing bonding diagrams

2009-11-03T20:50:21Z

Is it possible to import pre-existing assembly data (bonding diagrams) into VeloceWired? Which formats are supported?

Meet us at DesignCon 2010!

2010-01-15T09:38:40Z

DesignCon is the definitive event for electronic design experts spanning chip, package, board, and system domains, addressing common issues in signal integrity, power management, interconnection, and design verification.

http://www.designcon.com/2010/attendees/pages/helic.asp

Meet us at Booth #824.

Helic new RLCk Net extraction tool

2009-10-07T16:25:19Z

VeloceRaptor/X is a breakthrough RLCK extraction tool with unparalleled capacity and speed in the modeling of integrated passives such as transmission lines, interconnects, digital high-speed lines, spiral inductors and metal-insulator-metal (MIM) capacitors.The tool is powered by Helic’s renowned vector-based inductance modeling engine (VeloceRaptor™) which guarantees rapid EM model generation with no compromises in accuracy. As a layout extraction tool, VeloceRaptor/X contends and outperforms conventional EM simulators in terms of speed vs. accuracy. VeloceRaptor/X can be combined with Helic’s VeloceRF™ toolset to provide – for the first time – a complete solution for spiral inductor synthesis and wholechip modeling of RFICs and Systems-in-Package.

VeloceWired v1.5.5.3 release

2009-10-07T16:24:33Z

VeloceWired is a powerful package design tool providing rapid bondwire creation and extraction. With VeloceWired bondwire design becomes an integral part of the IC tool flow.

VeloceWired incorporates several attractive features such as :
• Accurate, broadband modeling of bondwire arrays.
• Seamless integration in Cadence Virtuoso® flow.
• Automatic annotation of parasitic inductances per wire.
• Supports a wide variety of bondwire profiles (JEDEC types and user-defined).
• Supports single-die, multi-die, stacked-die configurations.
• Automatic import of DXF package designs
• 3D view of die, package and bondwire interconnects
• Offers full integration with Helic VeloceRF™ (co-design of on-chip and off-chip inductors).

The latest VeloceWired version (v1.5.5.3) supports the model extraction option of specific bondwires, defined by the designer. In this way a reduced netlist can be generated, where only the bondwires of interest are involved.