Helic.com Forum

Development of a SoC noise integrity flow (in Greek)

2012-01-25T19:55:15+02:00

Προσκαλούμε ερευνητές (υποψήφιους διδάκτορες, post-doc) να συνεργαστούν μαζί μας στην ανάπτυξη ενός καινοτόμου περιβάλλοντος αναλύσεων θορύβου (noise integrity) σε εφαρμογές system-on-chip (SoC).

Η εργασία θα αξιοποιήσει σχετικές τεχνολογίες που αναπτύσσει η εταιρία, καθώς και άλλα βιομηχανικά εργαλεία ανάπτυξης SoC (Cadence, Synopsys).

Στο πλαίσιο της εργασίας θα δοθεί πρόσβαση σε κατασκευασμένα κυκλώματα και στο εργαστήριο μετρήσεων της Helic.

Οι ενδιαφερόμενοι παρακαλώ post reply (χρειάζεται register - link στο πάνω μέρος της σελίδας).

We announce customer wins in time for DAC 2011!

2011-05-31T15:54:16+02:00

Please watch our news section for the latest exciting news on industry adoption of Helic EDA products!

Key customer wins and product advances will be announced before and during DAC 2011 (San Diego, CA, 6-9 June 2011).

You may also want to follow me on Twitter...

ISSCC 2011 field report

2011-05-06T14:48:46+02:00

Please see my field report from ISSCC 2011 last February, seen through the lens of the high-speed and RF designer.

I would welcome your comments.

Sotiris

LTCC module design flow

2010-03-16T19:42:13+02:00

An earlier work on the subject, which describes a hardware demonstrator we developed a few years back to validate the concepts…

Editing symbols created by VeloceWired

2010-04-24T21:10:28+02:00

I would like to edit the symbol created during the model extraction step in VeloceWired. However I am unable to do so. Can you please explain how one can edit the symbol?

Available Bondwire Profiles in VeloceWired

2010-04-12T10:35:32+02:00

VeloceWired supports the widely used jedec-4 and jedec-5 formats, and also two types of generic format. The combination of jedec and generic types allows the user to efficiently approximate practically any type of bondwire (die-package, downdonds,die-die, stacked dies bonding, etc.).

For each bondwire profile several geometrical and physical parameters, such as diameter, height, angles, resistance can be defined, resulting in different model.

Bondwire Modeling

2010-04-12T10:23:21+02:00

VeloceWired features a rapid EM modeling engine, based on closed-form expressions that extract distributed netlists to model the performance of bondwire interconnects. Bondwire segments are represented as 3D vectors, and appropriate RLCk models are extracted.

The procedure enables rapid and accurate modeling of complex EM effects like:
- self inductance & resistance
- mutual inductance
- high frequency resistance (Skin Effect)
- capacitive coupling

An additional feature is the annotation of inductance values back into the layout. This is extremely useful as it provides the designer with an immediate “feeling” of what has been drawn so far. Thus the designer can easily quick-fix certain wires that are likely to hinder the circuit’s performance (e.g. too long wires that introduce large inductance, parallel wires with undesired magnetic coupling, etc).

Multi-die bonding

2010-04-12T10:07:42+02:00

I have a case of two dies that must be bonded in the same package. Also there are a lot of downbonding wires. Can i use VeloceWired for such an application?

Thanks

Compact Modeling with Guaranteed Passivity

2010-01-20T12:38:51+02:00

At the latest MOS-AK workshop that fringed the ESSCIRC/ESSDERC conference in Athens, I gave the following paper which provides a good overview of our unique modeling methodology and discusses model passivity and compaction issues.

Please find it on the MOS-AK web site in this link.

importing bonding diagrams

2009-11-03T20:50:21+02:00

Is it possible to import pre-existing assembly data (bonding diagrams) into VeloceWired? Which formats are supported?