Helic

Is VeloceRF being used in 45nm CMOS?

What does it take to design DRC clean spiral inductors in this node?

Hi Ulah,

VeloceRF is used in 45nm CMOS for quite some time (it’s over 2 years…)

It’s really tough to manually design DRC clean and DFM correct inductors and transformers in this node (it can take days or weeks…), but it’s just a simple click if you are using VeloceRF. VeloceRF supports automated inductor/transformer layouts tied to your technology and fully compliant with the demanding DRC and DFM requirements. Constraint-driven optimal synthesis is another key feature to help you meet your design requirements.

Do you work on 45nm CMOS? How do you deal with inductor design so far? Would you be interested in evaluating VeloceRF?

Thanks,
Padelis