Helic’s VeloceRF™ is selected by Fujitsu to build RFIC design flows for sub-100nm CMOS processes.

June 4, 2008

ATHENS, GREECE, June 4, 2007 – Helic S.A. proudly announces that Fujitsu Limited has adopted VeloceRF™ and Helic’s technology to build a new design-flow for RFICs in its 90nm and 65nm CMOS processes. The parties have agreed to develop world-class tooling and design methodology to support rapid prototyping and volume production of high-frequency ICs applying advanced lithography techniques.

Helic’s EDA tool, VeloceRF™ features a rapid and high-capacity vector-based RLCK modeling engine, the VeloceRaptor™, a powerful matching engine to support layout-vs.-schematic verification of any kind of integrated inductive component and a spiral inductor synthesizer, the Spiral Wizard™. The tool efficiently addresses DFM requirements emerging for RF CMOS at the 90nm process node and below. Features such as conductor track slotting to mitigate metal stress, geometry resizing under current density constraints and the use of dummy fill patterns are programmed in the VeloceRF™ parametric inductor library and are consistently supported by the Spiral Wizard™, the modeling engine and the layout and LVS modules.

The Spiral Wizard™ synthesis engine supports the creation of patterned shields to enhance inductor quality factor (Q) and improve substrate isolation. Generated inductor layouts are fully parametric and DRC-clean by design, easing adoption by foundries and design teams. VeloceRaptor™, the rapid, vector-based RLCK modeling engine is powered by a proprietary broadband skin-effect model, with demonstrated accuracy even above 40 GHz. The engine’s speed is class-leading and outperforms commercial EM simulators and shape-based extraction tools. Built-in netlist reduction keeps netlist sizes and simulation times at reasonable levels, without loss of model precision.

“First-time-right RF silicon has been a dream. We strongly believe the designer-centric methodology, the tools and the PDK adaptation we provide with Helic is the ultimate door opener to the whole new world of RF COT/ASIC,” said Mr. Tetsu Tanizawa, principle director, Technology & Business Foundation, Electronic Devices Business Group of Fujitsu Limited.

“Fujitsu leverages its leadership in sub-100nm CMOS silicon fabrication to foray the RFIC market and we are very proud to be part of the project. Their process engineering and EDA teams have challenged us to set higher standards for our product to address efficiently their needs,” said Dr. Yorgos Koutsoyannopoulos, CEO of Helic.

“Our new approach with Helic enables deeper and direct communication with customers on RF design issues in designer’s language, other than just a COT library support. Grounding, substrate noise, magnetic coupling are just a few among those critical effects that vary the true performance of RF circuits. Dynamic PDK support reflected in shorter design-time is the key for success,” said Dr. Yuu Watanabe, deputy general manager, Technology Development Division, Electronic Devices Business Group of Fujitsu Limited.

 

 

About Helic
Helic specializes in the development of enabling EDA technologies for RFIC and systems-in-package (SiP) design. Helic’s VeloceRF™ is the leading EDA tool for integrated inductor synthesis, modeling, and verification and has been adopted by several renowned semiconductor companies worldwide. With a global reach and sales offices in Europe, the U.S., and Japan, Helic offers its customers EDA tools, intellectual property (IP), and services that enable delivery of first-pass silicon, while greatly reducing the development cycle for complex wireless transceiver products. Helic is headquartered at 12 Sorou str., Marousi, GR-15125, Athens, Greece. For additional information please visit Helic at www.helic.com.

 

Editorial Contact:
Nikolas Provatas
T:+30 2109949390
E: N.Provatas@helic.com