HSPICE SIG 2018 event

April 3, 2018

Helic was invited to participate in the HSPICE SIG 2018 event at the Santa Clara Marriott that was held on Jan 31 2018. The event was well attended by key designers and design managers from the high speed digital and mixed signal design community. Helic’s message regarding the importance of chip-level EM aware physical verification sign-off resonated very well with the attendees. Technical presentations from companies like AMD on the challenges associated with high speed clock distribution networks dove-tailed well with Helic’s message. The unique combination of the high capacity/high accuracy EM model generation capability from Helic with the fast/high capacity circuit simulation capabilities from Synopsys seemed to resonate well with the need for efficient (in term of circuit simulation time and memory) simulation models that still maintain the accuracy needed for high performance SoC designs.