New release of VeloceRF™ supports 90-nm & 65-nm RFIC design
July 20, 2006
ATHENS, GREECE – Helic S.A. announces today the commercial availability of VeloceRF™ v1.5, featuring an enhanced Spiral Wizard™ inductor synthesizer, several improvements in its rapid RLCK modeling engine and new features addressing Design for Manufacturability (DFM) for 90-nm and 65-nm RFICs.
The Spiral Wizard™ synthesis engine in VeloceRF v1.5 now supports the creation of patterned shields that enhance inductor quality factor (Q) and improve substrate isolation. This capability is coupled with options to stack metal layers with distributed vias, to achieve good Q values even in low-cost processes that lack a thick inductor layer option. These tactics are not necessarily advantageous in all frequencies or for any spiral geometry, so the Spiral Wizard is equipped with the necessary intelligence to decide on their application, depending on user criteria and constraints. Generated inductor layouts are fully parametric and DRC-clean by design, easing adoption by foundries and design teams. Using the new Spiral Wizard, Helic demonstrated record-Q inductors that outperform published results, fabricated in an IDM customer’s SiGe BiCMOS process.
The new VeloceRF version efficiently addresses DFM requirements emerging for RF CMOS at the 90nm process node and below. Features such as conductor track slotting to mitigate metal stress, geometry resizing under current density constraints and the use of dummy fill patterns, are now programmed in the VeloceRF inductor library and are consistently supported by the Spiral Wizard, the modeling engine and the layout and LVS modules. VeloceRF™ v.1.5 has already been installed in the RFIC design flows of one 65-nm and five 90-nm IDM process design kits worldwide.
VeloceRaptor™, the rapid, vector-based RLCK modeling engine that powers VeloceRF now introduces a proprietary broadband skin-effect model, with demonstrated accuracy even above 30 GHz. Several improvements provide even better coverage of distributed capacitive and mutual inductance parasitics in complex layouts. The engine’s speed is class-leading, and outperforms all commercial EM simulators and shape-based extraction tools. Built-in netlist reduction keeps netlist sizes and simulation times at reasonable levels, without loss of model precision. Technology file setup has been made easier, reading directly from readily available foundry process stackup data.
VeloceRF continues to build on its acclaimed use model, being the only tool of its kind seamlessly integrated in the IC design flow with interfaces to leading LVS engines and circuit simulators. Helic’s FAE team comprises seasoned RFIC engineers that go beyond supporting an EDA tool, by acting as an extension to customer design teams.
Mr. Apostolos Liapis, Helic’s EDA Tools Manager commented on the new VeloceRF release: “With this version we manage to keep abreast of customer needs and address properly problems that have surfaced in the past year or so, with RFIC designs entering the 90-nm node. Keys to success have been the long-term collaboration with lead customers and our continuous research on modeling algorithms and design flow improvements.”
Helic will provide the new version of VeloceRF to all existing customers under maintenance contracts free of charge.
Information on VeloceRF available at: www.helic.com/products/VeloceRF
Helic S.A. specializes in the development of enabling EDA technologies for RFIC and System-in-Package design. Helic’s VeloceRF™ is the leading EDA tool for spiral inductor synthesis, modeling and verification and has been adopted by several renowned semiconductor companies worldwide. With a global reach and sales offices in Europe, US and Japan, Helic offers to its customers EDA tools, IP and services that enable delivery of first-pass silicon, while greatly reducing the development cycle for complex wireless transceiver products. For additional information please visit Helic online at www.helic.com.