Helic, Wipro and NXP joint presentation: An EM-Aware Methodology for a High-Speed Multi-Protocol 28Gps SerDes Design with TSMC 16FFC

BY MAGDY ABADIR, October 26, 2017 in Semiconductor Engineering

Helic has a longstanding relationship with the Wipro High-Speed SerDes Analog & Mixed-signal Design Team that develops IP for the NXP Digital Networking business unit.

As SerDes design has become increasingly challenging mainly due to data rates pushing past 10Gbps and up to 56Gbps, Helic and NXP decided to take the stand in the recent TSMC Open Innovation Platform Forum N. America, held in Santa Clara on Septemberr 13th, 2017, to present how their collaboration has led to multiple generations of successful first-pass SerDes IP families for NXP and Continuous improvements to the Helic suite of tools.

To achieve demanding performance requirements driven by the protocol specifications, it is common for designers to use on-chip inductors to implement filtering techniques in the transmitter and receiver data lanes as well as low noise LC-tank oscillators for PLL lanes. The increase of internal clock frequencies and data rates requires that Electromagnetic (EM) phenomena, like parasitic inductance and magnetic coupling, can no longer be ignored in such designs. The faster the data rate/clock speed, the more difficult it is to predict and manage unwanted behaviour due to such phenomena. In order to overcome these design challenges there is a need for a new design methodology which includes an EM modeling engine that has the following key features:

  • Very high capacity with no compromise in accuracy
  • Very fast extraction times (comparable to RC parasitic extraction engines)
  • Tight integration into the Custom IC design flow. I.e. seamless interface with both front-end (layout, schematic editors) and back-end (LVS/RCX) tools

Traditional EM solvers fall far short of the requirements stated above. They are typically unable to deal with the high complexity and dense metallization of an analog and mixed-signal design like a 28Gbps SerDes. Having been designed primarily to model passive spiral structures with a few ports (typically less than 10), the size and complexity of the metallization that needs to be extracted in these designs easily overwhelms the capacity of traditional EM tools. Massive networks of interconnects, ground networks and power grids comprising of hundreds of ports are totally out of their scope.

The Wipro design team recently developed and tested silicon for a 28Gbps SerDes system for NXP that features simultaneous multi-lane and multi-protocol support. The SerDes IP is implemented with TSMC’s 16nm FINFET process which helps to control costs and power for high-performance designs. This system integrates 8 data lanes and 2 PLL lanes containing 4 LC voltage controlled oscillators (LC-VCOs) that support data rates from 28G to 16G, 10G, 5G and below. Various Helic generated and modeled structures are implemented in the data and PLL lanes as well as the global clock distribution network.

In the joint presentation, Helic and Wipro’s High-Speed SerDes Analog & Mixed-signal Design Team describe their collaboration and a design methodology that has resulted in multiple generations of first-pass success SerDes IP families for NXP (using TSMC’s 28nm and 16nm process nodes as well as other technologies). Wipro employs Helic’s VeloceRF and RaptorX software comprising a complete EM-aware design methodology that starts from optimal, DRC-clean spiral device synthesis and floor-planning, introduces EM-extraction in-the-loop and closes the flow with EM-signoff post-LVS. Helic’s tools are being used in the flow to capture electromagnetic coupling effects between spiral passives, interconnects, power and signal lines and the power grid, from the earliest design stages leading to compact circuit sizes and notably shorter design cycles.

“The seamless integration of Helic’s software suite in TSMC 16nm PDKs and the Cadence Custom IC design flow improves productivity and data management. These benefits enable Wipro’s team to meet accelerated time-to-market challenges with no performance compromise.”, noted Bud Hunter, SerDes Analog IC Design Manager at Wipro.

“Helic is a highly valued tool vendor and integral part of the design flow for the Digital Networking business unit at NXP, spanning multiple generations of successful SerDes IP development”, said David Bearden, technical fellow and analog design manager for NXP Digital Networking.