Preparing For Electromagnetic Crosstalk Challenges
February 13, 2018
Electromagnetic (EM) coupling/noise is not a new phenomenon, but increasing bandwidth and decreasing size, along with low-power demands of today’s electronic systems is making EM crosstalk a first order challenge. At clock frequency of 10GHz+ and data rate of 10Gbps+, parasitic inductance and inductive coupling that were previously safe to ignore are no longer. System-on-chip (SoC) at 16nm and below places complex high speed digital circuitry, analog and RF blocks very close together, creating opportunities for EM crosstalk inside these components, as well as across various blocks.
EM crosstalk is an unwanted interference caused by the electrical field (capacitive) and magnetic field (inductive) of one or more signals (aggressor) affecting another signal (victim). Capacitive coupling is stronger at close proximity and fades out at a longer distance, allowing analysis on a limited scope of the design. However, a magnetic field can travel along relatively large loops that are formed by structures outside the immediate neighborhood of victim signals and can even encircle the entire layout of the chip. This requires a complete EM model of the signal nets in interest, putting significant burden on existing tools.
For accurate analysis of EM crosstalk, all design elements that can contribute to potential EM noise, including power/ground nets, silicon substrate, package layers, bond/bump pads, seal rings, metal fill and decoupling capacitance, should be extracted, modeled and analyzed. Typically, these structures have complex physical layouts that need to be properly meshed to extract resistance, coupling capacitance, inductance and mutual inductance. With the goal of generating full and accurate EM model of the design, these models need to be presented in several forms such as S-parameter model, state-space matrices, rationally fitted model or a full RLCK model for analysis by the downstream tools.
To solve EM crosstalk challenges, it is essential to accurately model all types of surrounding structures.
Appropriate modeling of the complex environment of advanced node SoCs to identify and mitigate EM crosstalk problems can be quite challenging. Often times, the requirements are inherently contradictory. On the one hand, the models need to be EM accurate from DC to the 3rd harmonic of the highest frequency component of a signal (for a 10GHz clock this can be well into mm-wave region), and at the same time the model should be easily simulateable by circuit simulators both in the time and frequency domain. To address this, it is essential to create a passive, causal netlist-based model that is broadband or an S-parameter file that is DC accurate or, ideally, both!
Another key technology requirement is the ability to handle several hundreds to several thousands of ports. Traditional EM tools tend to be quite limited in the number of ports in the model – this limitation effectively rules them out as candidates for use with complex SoCs. In a similar vein, the number of metal shapes/nets and the complexity of these shapes is extremely high – this again imposes the need for very high capacity while managing the contradictory requirement of easily simulateable models. Sophisticated model order reduction techniques become essential.
Advanced process nodes impose even more difficult requirements. Stackups in use today often include up to 100 dielectric layers and incredibly complex fill patterns – this creates extremely complex, fully distributed electric field patterns that are not easy to model. Accurate modeling of capacitance in these cases is extremely challenging – traditional EM methods fail to scale and even pattern matching-based parasitic extraction technologies, while fast, are struggling to provide the accuracy needed. In addition, at these advanced nodes, layout dependent effects play a significant role in the physically realized design. Significant differences between the drawn metal shapes and the actual metal shapes can mean that the model for the drawn shapes can be more than 15% off compared to reality unless these effects are accounted for prior to modeling. A fast, scalable and accurate field solver method that includes the ability to model the most advanced LDE effects becomes critical.
An effective solution requires combination of highest capacity with intelligent handling of all design layout details. Capacity limitations or memory/runtime constraints can lead to sacrificing important details about the design and surrounding environment. This can mask the effect of EM crosstalk or lead to a wrong conclusion. Maintaining accuracy is vital, but extreme levels of detail may only be needed in critical parts of the layout. Thus, the ability to automatically operate in a hybrid extraction mode will help achieve high-accuracy while maintaining reasonable extraction and modeling speed.
Over the past few years, driving factors such as increasing speed, higher levels of integration, lower power requirements and advanced packaging technologies have raised EM crosstalk as a critical design issue that can no longer be designed out or ignored. Doing so is highly risky and can have significant impact on time and cost. Therefore, it is essential to start adopting methodologies that can identify and manage EM crosstalk.
Anand Raman is the director of technical marketing at Helic.
The article was originally published here.