Taking Inductance And Electromagnetic Effects More Seriously
August 22, 2018
With increasing frequencies, tighter margins, denser integrated circuits, new devices and materials, the necessity of full EM analysis including magnetic/inductive effects is becoming a fundamental question for the industry.
Where and when should full EM verification be included? Can some of major chip failures during development be attributed to ignoring magnetic effects? Is the methodology of applying best practices to avoid EM coupling, and skipping the tedious EM verification part, still a valid practice? Is this methodology scalable to future integrated circuits? Are the dense matrices resulting from inductive coupling and difficulty of simulations why the industry did not widely adopt full EM simulations? And what can be done in-terms of tool development, education, and research to lower the barrier for industry to adopt full EM simulation?
The above topics were debated and discussed by a distinguished panel of industry leaders at DAC (and moderated by Professor Yehea Ismail). The Panel included Baribrata Biswas, R&D Vice President in Synopsys’ Design Group, Ron Ho, Senior Director of Intel’s Programmable Solutions Group (PSG), Vishnu Balan, Senior Director of Mixed-Signal Design at Nvidia, and Yorgos Koutsoyannopoulos, CEO of Helic Corp.
The panel members all agreed strongly that full EM analysis is becoming fundamental in at least some parts of any cutting-edge chip. Bari was of the opinion that it’s needed in some key places in a chip such as clocking, wide data buses, and power distribution, but not yet in mainstream digital design. Ron was of the opinion that for current chips, applying best practices and skipping using full EM simulations still works. However this methodology will not scale into the future. Vishnu simply stated that EM simulation is a must with very high frequency SerDes designs. And Yorgos agreed strongly with Vishnu, showing a couple of examples of faraway structures where strong EM coupling unexpectedly occurred, causing failures in key chips.
Yehea was of the opinion that strong magnetic effects are already there, and have been very significant in integrated circuits for awhile. But the difficulty of including magnetic effects into simulation is the main reason full EM verification is not mainstream yet. Everyone agreed that not including EM effects in verification results in over-design at best, and potential failures in the worst cases.
The panel agreed there is a need for significant improvement of tools that handle EM verification, better understanding of magnetic effects, and significant research on how to protect against EM failures or even adopt designs that benefit from magnetic effects. The panel also agreed that current trends of higher frequencies, denser circuits, and scaling of devices combined with the exploding penalty on a chip failure, makes including full EM verification imperative.
—Ismail Yehea is a professor in the Department of Electronics and Communications Engineering at The American University in Cairo.