Is It Time To Take Inductance And Electromagnetic Effects On SoCs Seriously?

BY MAGDY ABADIR, June 14, 2018 in Semiconductor Engineering

Electromagnetic (EM) crosstalk impact on SoC performance has been a topic of discussion for a number of years, but how seriously have designers put EM crosstalk detection and avoidance into their SoC design practice? With increasing demand for faster bandwidth, lower power and higher density electronic systems, isn’t it about time to take inductance and EM effects seriously? This topic will be discussed by panel of industry leaders at the upcoming Design Automation Conference (DAC) in San Francisco.

One set of experts argue that internally-created EM crosstalk is only important in analog/RF designs and is less of an issue with today’s large mixed-signal SoCs. They also believe that inductance modeling is not critical for accurately assessing the impact of crosstalk on timing and power, and that RC extraction is sufficient. They feel that this, combined with adding margin or adopting design techniques that minimizes the inductance effect, should be good enough.

Another camp of experts argues that increased integration of complex high speed digital, analog and RF IP blocks within SoCs has created new opportunities for EM crosstalk, whether inside complex IP blocks or across various blocks. In addition, a decrease in signal voltage levels driven by lower power trends, as well as architectural design trends such as placing massively parallel high-speed serial channels or multiple high-speed clock networks on a single chip are contributing to EM crosstalk. The renewed escalation of clock frequencies and data rates in emerging cutting-edge chips means inductance effects will be much more prominent in those chips since the inductive impedance is proportional to frequency.

So, which group of experts’ assessments does a designer follow for their next SoC project?

EM crosstalk is defined as unwanted interference caused by electric and magnetic fields of one or more signals (aggressors) affecting another signal (victim). Capacitive crosstalk is caused by electrical field, which is stronger at close proximity and fades out at a longer distance. This limits the scope and reduces modeling requirements, allowing existing RC-based analysis tools to sufficiently determine the impact of crosstalk on timing and power.

However, inductive coupling is caused by magnetic fields, which can travel along relatively large loops formed by structures outside the immediate neighborhood of the victim signal and can even encircle the entire layout of the chip. The net result is a potentially large number of aggressors adding up noise in some switching conditions at the location of a victim net. Shielding against magnetic coupling is much harder than electric coupling because the relative permeability of the interconnect is practically one, making interconnects virtually nonexistent in terms of magnetic fields. This increase in scope requires analysis tools that are capable of accurately modeling all design structures including power/ground nets, silicon substrate, package layers, bond/bump pads, seal rings, metal fill and decoupling capacitance. Also, in these complex structures, inductance and mutual inductance have bigger impact and should be included.

One of the biggest challenges is that EM crosstalk induced problems do not neatly package themselves into a single signature failure such as timing. Often times, it manifests itself as a degradation in some key performance criterion that varies from design to design. EM crosstalk can impact delay in unpredictable manner, increase jitter, distort key signals and create variety of system level problems. It is very difficult to identify, isolate and mitigate inductive coupling induced failures, especially without considering inductance/mutual inductance and all design elements across the entire chip.

Another approach is to “design out” inductance by using techniques such as differential switching on busses to cancel out the coupling noise or “overdesign” high-speed/sensitive lines by adding buffers or shields to minimize the impact of EM crosstalk. But these methods can result in a chip with sub-optimal performance and higher cost and risk. In fact, circuits with dominant inductive effects as compared to circuits with dominant resistive effects always exhibit much better performance in terms of speed, waveform shape, and power consumption.

Is EM crosstalk in SoC a real problem that needs to be taken seriously? Join a panel of experts from Intel, Nvidia, Synopsys and Helic, moderated by professor Yehea Ismail from the American University of Cairo, as they answer questions such as “is inductance modeling required in advanced mixed-signal SoC design?”, “can we continue to ignore inductance and rely on adding margin?”, and “at what technology/frequency should we worry about EM crosstalk?”

Is It About Time To Take Inductance And Electromagnetic Effects On SoC Seriously? will be held Thursday June 28 at 3:30pm – 4:25pm in Room 3020.