Blog

  • Aging In Advanced Nodes

    L-R: João Geada, Hany Elhak, Christoph Sohrmann, Magdy Abadir; Mick Tegethoff; Naseer Khan. SE: What do design teams need to know about aging and reliability to make sure that those designs will do what they need to do? Geada: There are fundamentally two things that need to be dealt with, and one of them is really […]

  • Enabling Cheaper Design

    While the EDA industry tends to focus on cutting edge designs, where design costs are a minor portion of the total cost of product, the electronics industry has a very long tail. The further along the tail you go, the more significant design costs become as a percent of total cost. Many of those designs […]

  • The Rising Cost Of 5G

    Semiconductor Engineering sat down to talk about challenges and progress in 5G with Yorgos Koutsoyannopoulos, president and CEO of Helic; Mike Fitton, senior director of strategic planning and business development at Achronix; Sarah Yost, senior product marketing manager at National Instruments; and Arvind Vel, director of product management at ANSYS. What follows are excerpts of that conversation. To view […]

  • Minimizing The Risk Of Electromagnetic Crosstalk Failures

    Leading semiconductor markets, such automotive, machine learning, large scale computing and networking, are driving the need for high density chips that integrate high performance digital cores with sensitive analog/RF IP, while operating at the lowest power and fastest bandwidth possible. These trends are increasing the sensitivity to electromagnetic (EM) coupling, and requiring designers to worry […]

  • Taking Inductance And Electromagnetic Effects More Seriously

    With increasing frequencies, tighter margins, denser integrated circuits, new devices and materials, the necessity of full EM analysis including magnetic/inductive effects is becoming a fundamental question for the industry. Where and when should full EM verification be included? Can some of major chip failures during development be attributed to ignoring magnetic effects? Is the methodology […]

  • Is It Time To Take Inductance And Electromagnetic Effects On SoCs Seriously?

    Electromagnetic (EM) crosstalk impact on SoC performance has been a topic of discussion for a number of years, but how seriously have designers put EM crosstalk detection and avoidance into their SoC design practice? With increasing demand for faster bandwidth, lower power and higher density electronic systems, isn’t it about time to take inductance and […]

  • IP Electromagnetic Crosstalk Requires Contextual Signoff

    Continuous advancement in technology scaling is enabling the emergence of high-performance application markets such as artificial intelligence, autonomous cars and 5G communication. These electronic systems operate at multi-GHz speed, while consuming the lowest amount of power possible leaving very little margin for error. Chips in these systems are highly integrated with multiple noise sensitive analog […]

  • Preparing For Electromagnetic Crosstalk Challenges

    Electromagnetic (EM) coupling/noise is not a new phenomenon, but increasing bandwidth and decreasing size, along with low-power demands of today’s electronic systems is making EM crosstalk a first order challenge. At clock frequency of 10GHz+ and data rate of 10Gbps+, parasitic inductance and inductive coupling that were previously safe to ignore are no longer. System-on-chip […]

  • Mixed-Signal Issues Worse At 10/7nm

    Despite increasingly difficulty in scaling digital logic to 10/7nm, not all designs at the leading edge are digital. In fact, there are mixed-signal components in designs at almost all nodes down to 10/7nm. This may seem surprising because analog scaling has been an issue since about 90nm, but these are not traditional analog components. Analog […]

  • SoC Electromagnetic Crosstalk: From A Tool Perspective

    Why most of the commercial electromagnetic solvers and extraction engines are not suitable for analyzing EM crosstalk in a typical SoC design.   Most commercial electromagnetic (EM) solvers are limited by the size of the design that they can handle, or they may take a very large amount of time or memory to perform the […]