Power Delivery Affecting Performance At 7nm


    Complex interactions and dependencies at 7nm and beyond can create unexpected performance drops in chips that cannot always be caught by signoff tools. This isn’t for lack of effort. The amount of time spent trying to determine if an advanced-node chip will work after it is fabricated has been rising steadily for several process nodes. […]

    Electromagnetic Analysis And Signoff: Cost Savings

    BY Nikolas Provatas and Magdy Abadir

    We are often asked by SoC design teams about the benefits of an electromagnetic analysis and signoff methodology. Here is an overview of some of the big “cost savings”. Time to Market Savings Utilizing an EM crosstalk analysis and signoff methodology provides designers with an “insurance policy” against the risk of EM coupling in their […]

    New Shifts In Automotive Design


    Four big shifts in automotive design and usage are beginning to converge—electrification, increasing connectivity, autonomous driving and car sharing—creating a ripple effect across the automotive electronics supply chain. Over the past few years the electronic content of cars and other vehicles has surged, with electrical systems replacing traditional mechanical and electro-mechanical subsystems. That has been […]

    High-Performance Memory Challenges


    Designing memories for high-performance applications is becoming far more complex at 7/5nm. There are more factors to consider, more bottlenecks to contend with, and more tradeoffs required to solve them. One of the biggest challenges is the sheer volume of data that needs to be processed for AI, machine learning or deep learning, or even […]

    The Trouble With Models


    Models are becoming more difficult to develop, integrate and utilize effectively at 10/7nm and beyond as design complexity, process variation and physical effects add to the number of variables that need to be taken into account. Modeling is a way of abstracting the complexity in various parts of the semiconductor design, and there can be […]

    Predictions: Manufacturing, Devices And Companies


    Some predictions are just wishful thinking, but most of these are a lot more thoughtful. They project what needs to happen for various markets or products to become successful. Those far reaching predictions may not fully happen within 2018, but we give everyone the chance to note the progress made towards their predictions at the […]

    Turning Down The Power


    Chip and system designers are giving greater weight to power issues these days. But will they inevitably hit a wall in accounting for ultra-low-power considerations? Performance, power, and area are the traditional attributes in chip design. Area was originally the main priority, with feature sizes constantly shrinking according to Moore’s Law. Performance was in the […]

    Lots Of Little Knobs For Power


    Dynamic power is becoming a much bigger worry at new nodes as more finFETs are packed on a die and wires shrink to the point where resistance and capacitance become first-order effects. Chipmakers began seeing dynamic power density issues with the first generation of finFETs. While the 3D transistor structures reduced leakage current by providing […]

    Noise Abatement

    BY Brian Bailey

    Noise is a fact of life. Almost everything we do creates noise as a by-product and quite often what is a signal to one party is noise to another. Noise cannot be eliminated. It must be managed. But is noise becoming a larger issue in chips as the technology nodes get smaller and packaging becomes […]

    New Power Concerns At 10/7nm


    As chip sizes and complexity continues to grow exponentially at 7nm and below, managing power is becoming much more difficult. There are a number of factors that come into play at advanced nodes, including more and different types of processors, more chip-package decisions, and more susceptibility to noise of all sorts due to thinner insulation […]

    Multi-Physics Combats Commoditization


    The semiconductor industry has benefited greatly from developments around digital circuitry. Circuits have grown in size from a few logic gates in the 1980s to well over 1 billion today. In comparison, analog circuits have increased in size by a factor of 10. The primary reason is that digital logic managed to isolate many of […]

    The Week In Review: Design


    M&A Synopsys finalized its acquisition of Black Duck Software, which provides software for managing and securing open source software in projects, adding to Synopsys’ burgeoning software analysis and security business. The cash deal was approximately $547 million net of cash acquired. STMicroelectronics acquired Atollic, maker of the Eclipse-based TrueSTUDIO Integrated Development Environment (IDE) for embedded development on Arm-based devices and […]


    How To Make Sure IP Will Float In The Rough SoC Sea


    Today a typical SoC includes hundreds of instances of IP modules both digital and analog. These IPs are typically verified individually by the vendors. The burden of guaranteeing functionality when placed in the midst of a monster SoC is typically left to the SoC owner. With increasing frequencies, tighter margins, denser integrated circuits, new devices […]

    Aging In Advanced Nodes


    L-R: João Geada, Hany Elhak, Christoph Sohrmann, Magdy Abadir; Mick Tegethoff; Naseer Khan. SE: What do design teams need to know about aging and reliability to make sure that those designs will do what they need to do? Geada: There are fundamentally two things that need to be dealt with, and one of them is really […]

    Enabling Cheaper Design


    While the EDA industry tends to focus on cutting edge designs, where design costs are a minor portion of the total cost of product, the electronics industry has a very long tail. The further along the tail you go, the more significant design costs become as a percent of total cost. Many of those designs […]

    The Rising Cost Of 5G


    Semiconductor Engineering sat down to talk about challenges and progress in 5G with Yorgos Koutsoyannopoulos, president and CEO of Helic; Mike Fitton, senior director of strategic planning and business development at Achronix; Sarah Yost, senior product marketing manager at National Instruments; and Arvind Vel, director of product management at ANSYS. What follows are excerpts of that conversation. To view […]

    Minimizing The Risk Of Electromagnetic Crosstalk Failures


    Leading semiconductor markets, such automotive, machine learning, large scale computing and networking, are driving the need for high density chips that integrate high performance digital cores with sensitive analog/RF IP, while operating at the lowest power and fastest bandwidth possible. These trends are increasing the sensitivity to electromagnetic (EM) coupling, and requiring designers to worry […]

    Taking Inductance And Electromagnetic Effects More Seriously

    BY Magdy Abadir and Yehea Ismail

    With increasing frequencies, tighter margins, denser integrated circuits, new devices and materials, the necessity of full EM analysis including magnetic/inductive effects is becoming a fundamental question for the industry. Where and when should full EM verification be included? Can some of major chip failures during development be attributed to ignoring magnetic effects? Is the methodology […]

    Is It Time To Take Inductance And Electromagnetic Effects On SoCs Seriously?


    Electromagnetic (EM) crosstalk impact on SoC performance has been a topic of discussion for a number of years, but how seriously have designers put EM crosstalk detection and avoidance into their SoC design practice? With increasing demand for faster bandwidth, lower power and higher density electronic systems, isn’t it about time to take inductance and […]

    IP Electromagnetic Crosstalk Requires Contextual Signoff

    BY Magdy Abadir

    Continuous advancement in technology scaling is enabling the emergence of high-performance application markets such as artificial intelligence, autonomous cars and 5G communication. These electronic systems operate at multi-GHz speed, while consuming the lowest amount of power possible leaving very little margin for error. Chips in these systems are highly integrated with multiple noise sensitive analog […]

    Preparing For Electromagnetic Crosstalk Challenges

    BY MAGDY ABADIR and Anand Raman

    Electromagnetic (EM) coupling/noise is not a new phenomenon, but increasing bandwidth and decreasing size, along with low-power demands of today’s electronic systems is making EM crosstalk a first order challenge. At clock frequency of 10GHz+ and data rate of 10Gbps+, parasitic inductance and inductive coupling that were previously safe to ignore are no longer. System-on-chip […]

    Mixed-Signal Issues Worse At 10/7nm


    Despite increasingly difficulty in scaling digital logic to 10/7nm, not all designs at the leading edge are digital. In fact, there are mixed-signal components in designs at almost all nodes down to 10/7nm. This may seem surprising because analog scaling has been an issue since about 90nm, but these are not traditional analog components. Analog […]

    SoC Electromagnetic Crosstalk: From A Tool Perspective


    Why most of the commercial electromagnetic solvers and extraction engines are not suitable for analyzing EM crosstalk in a typical SoC design.   Most commercial electromagnetic (EM) solvers are limited by the size of the design that they can handle, or they may take a very large amount of time or memory to perform the […]

    Electromagnetic (EM) Crosstalk Analysis: Unlocking the Mystery


    Ignoring electromagnetic crosstalk is highly risky and can cause significant time-to-market delays as well significant cost over runs. Most current SoC design flows fundamentally ignore inductance and EM effects, and the term “EM crosstalk analysis” may sound Greek to them. This short article provides a quick overview of the basic steps involved in doing EM […]

    Crosstalk Analysis At 7nm


    Faster speed and smaller features are increasing the noise volume. The increasing demand for electronic systems with increasing bandwidth and decreasing size puts more high-speed circuitry and high bandwidth channels in ever-closer proximity. The continuous increase in internal clock frequencies (e.g. 5 – 10 GHz) and the increase in data rates (e.g. >10Gbps) are fueling […]

    Electromagnetic (EM) Crosstalk: Challenges and Trends


    Abstract— With the advent of advanced technologies and System on-Chip (SoC) architectures, ignoring electromagnetic crosstalk is highly risky resulting in significant delays in reaching the market on time as well significant cost over runs. This short article provides a quick definition of electromagnetic crosstalk, in the context of modern SoC designs, and the technology and […]

    Noise Issues At 10nm And Below


    Most of the conversations below 10nm have been about lithography, materials and design constraints. But as companies push to 7nm and beyond, they are faced with a host of new challenges, including how to deal with electromagnetic crosstalk. Electromagnetic crosstalk is unwanted interference caused by the electric and magnetic fields of one or more signals […]


    Helic, Wipro and NXP joint presentation: An EM-Aware Methodology for a High-Speed Multi-Protocol 28Gps SerDes Design with TSMC 16FFC


    Helic has a longstanding relationship with the Wipro High-Speed SerDes Analog & Mixed-signal Design Team that develops IP for the NXP Digital Networking business unit. As SerDes design has become increasingly challenging mainly due to data rates pushing past 10Gbps and up to 56Gbps, Helic and NXP decided to take the stand in the recent […]

    Interview with Helic CEO in EDACafe – Helic: Blending the Long View with Pragmatic Realities


    Taking guidance from their website, Silicon Valley based Helic provides “EDA software that mitigates the risk of electromagnetic crosstalk in high-speed and low-power SOC designs.” The company’s products include VeloceRF, an inductive device compiler and modeling tool which provides DRC clean devices for geometries as low as 10 nanometers; RaptorX, a pre-LVS electromagnetic modeling tool; […]

    White Paper: Challenges and Trends in SOC Electromagnetic (EM) Crosstalk


    Electromagnetic Crosstalk analysis is emerging as a fundamental necessity as a component of electronic system development. With the advent of advanced technologies and System on-Chip (SoC) architectures, ignoring electromagnetic crosstalk is highly risky resulting in significant delays in reaching the market on time as well significant cost over runs. This paper provides an overview of […]


    Tech Talk: 7/5/3nm Signoff


    Anand Raman, director of technical marketing at Helic, explains what’s needed to improve confidence in designs at the most advanced process nodes.

    Tech Talk: EM Crosstalk


    An issue previously confined to analog circuits has become a critical design consideration for digital designs at 10/7nm. Anand Raman, senior director at Helic, talks about the impact of electromagnetic interference on digital design at 10/7nm and beyond. Once confined to the analog space, noise is suddenly an issue at advanced nodes for all designs. […]