Helic

VeloceWired® is a powerful package design tool providing rapid bondwire creation and extraction. With VeloceWired® bondwire design becomes an integral part of the IC tool flow. Featuring a rapid modeler that allows full RLCK extraction of bondwire interconnects in mere seconds, VeloceWired® enables the co-design of high-speed circuitry with the package and bridges the related gap in parasitics sign-off. VeloceWired® gives the IC designer control over the package, and helps you reach an optimal design down to the pin.

Bondwire design in the flow

VeloceWired® features an efficient and flexible bondwire editor that works seamlessly inside Cadence®Virtuoso®. Bondwires are created in 2-D through a simple point-and-click procedure, while their 3-D properties can be edited on-the-fly. Die-to-die and stacked-die configurations are supported. Moving or rotating the die or the package will automatically resize and redraw any bondwires you have created; you can then extract and re-simulate in seconds. The creation and optimization of bondwires has never been so simple!

Bondwire Modeling

The modeling engine of VeloceWired® enables full RLCk extraction of bondwire interconnects. The respective distributed model is generated in seconds, and captures complex electromagnetic effects such as self and mutual inductances, frequency-dependent resistance and capacitive coupling. A wide variety of bondwire profiles (Jedec types and user defined) are supported, allowing the accurate modeling of virtually any type of interconnect
(die-package, multi-die, stacked die).

Features

• Seamless integration in Cadence® Virtuoso®Layout and Schematics
• Integration with Helic VeloceRF for co-design of on-chip and off-chip inductors
• Accurate, broadband modeling of bondwire arrays
• Automatic annotation of self and mutual inductances on the layout
• Wide variety of bondwire profiles (Jedec types and user defined)
• Injection mould dielectric effects included
• Single-die, multi-die, stacked-die configurations